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    Portada » Estudios » Formación Permanente - Microcredenciales » RISC-V: Architecture and Design based on Commercial VeeR Cores on FPGA (11/05/2026-17/07/2026) (CXCU-M1232601)

RISC-V: Architecture and Design based on Commercial VeeR Cores on FPGA (11/05/2026-17/07/2026) (CXCU-M1232601)

Formación Permanente - Microcredenciales. Curso 2025/2026.

Duración

6 ECTS

Plazas

12

Importe de matrícula

120 €

Contenido del curso

  • RISC-V is an Instruction Set Architecture (ISA) created with the goal of becoming a universal ISA.
  • This course aims to introduce students to the use of this architecture, bridging the gap between the existence of an open architecture and its practical use in the implementation and programming of processors based on it.
  • The course begins with an extensive introduction to RISC-V architecture and assembly programming, continues with a series of Input/Output labs, and concludes with a detailed study of two processors widely used in the commercial domain — VeeR EL2 and VeeR EH1 — all implemented on Xilinx FPGA boards.