Functional Verification of Digital Integrated Circuits using UVM Methodology - Semipresencial (16/03/2026 - 29/05/2026) (CXD4 - M1262601)

Formación Permanente - Microcredenciales. Curso 2025/2026.

6 ECTS

120 €

This course provides an introduction to advanced verification methodologies for digital integrated circuits using the Universal Verification Methodology (UVM).
It assumes that participants have a prior understanding of hardware description languages and includes a concise overview of SystemVerilog before focusing on the development and implementation of UVM-based verification environments.
The program comprises 45 hours, delivered through 50% in-person sessions and 50% practical, tool-based activities aligned with current industrial practice.