This course explores High-Level Synthesis (HLS) methods and processes for designing efficient digital circuits, with an emphasis on hardware/software acceleration for data-intensive applications. As digital circuits grow in size and complexity, traditional hand-coded RTL design has become a significant bottleneck, slowing development cycles. Meanwhile, modern AI, ML, and DSP algorithms demand high parallel computing performance with low power consumption, challenging designers to produce hardware solutions with optimized power, performance, and area
(PPA) metrics at unprecedented speeds.